Lock or locked loop circuits, such as phase locked-loop (PLL) and delay locked-loop (DLL) circuitry, are widely used as clock generators for a variety of applications including microprocessors, wireless devices, serial link transceivers, disk drive electronics, and so forth. FIG. 1 illustrates a typical charge pump based PLL circuit 110 that may include phase frequency detector PFD 110, charge pump CP 120, loop filter LPF 130, voltage control oscillator VCO 140, and dividers/M 150 and/N 152.
The PLL 100 of FIG. 1 has a voltage control oscillator VCO 140 that generates an output clock CKOUT that is frequency locked and phase aligned with an input clock CKIN due to the negative feedback loop. The output clock frequency is defined by the equation CKOUT=CKIN*(N/M), when the PLL 100 is in the lock condition. The inputs ckref and ckfb of the phase frequency detector PFD will be phase aligned to each other.
As illustrated in circuit 200 of FIG. 2, a clock tree 220 may be added at the output of the PLL/DLL 210. The output of the clock tree QK is required to be phased aligned with CKIN. FIG. 2 is a simplified version of a PLL/DLL with a clock tree where M=1 and N=1.
FIG. 3A illustrates a block diagram of an example phase lock loop circuit having Duty Cycle Correction (DCC) circuitry at the output, outside the loop, as known in the art.
Referring to FIG. 3A, a prior art of PLL/DLL with Duty Cycle Correction (DCC) near QK is shown. In this case, DCC is outside PLL loop.
FIG. 3B illustrates a block diagram of an example phase lock loop circuit having Duty Cycle Correction (DCC) circuitry within the loop, coupled directly between the PLL and the clock tree circuitry, as known in the art. Referring to FIG. 3B, another prior art PLL/DLL is shown, including Duty Cycle Correction (DCC) circuitry directly at the output of PLL, before the clock tree.
As set forth below, one or more exemplary aspects of the disclosure may overcome such shortcomings and/or otherwise impart innovative aspects by, for example, providing circuitry that reduces skew between an input clock and a plurality of clock tree outputs.